A Timing Synchronization Algorithm in Ultra-high-speed System Based on FPGA

Abstract

This essay will present an implementation of ultra-high-speed timing synchronization based on FPGA, it can break the rate limitation of digital device in algorithm and use a fully-pipelined structure with maximum throughput in model level at less hardware cost, which largely improves the data throughput in timing synchronization. This algorithm is applicable to any “amplitude-phase†joint modulation such as BPSK, QPSK, 8PSK, 16QAM and 32APSK, it can also be expanded to higher rate use, so it has wide application prospect in satellite-ground and satellite-satellite high capacity network as well as onboard ultra-high-speed video and image systems.